1. Field
The present invention relates in general to the field of verifying logic circuit designs, which are especially used in processor systems, and in particular to a method and a system for verification of logic circuit designs using dynamic clock gating, wherein the logic circuit design comprise processors, cores, units, macros and/or sub macros for example. Still more particularly, the present invention relates to a data processing program and a computer program product for verification of logic circuit designs using dynamic clock gating.
2. Description of the Related Art
Dynamic clock gating is one method for minimizing the power consumption of logic circuitries which are used in electronic devices. The main idea is to disable clocking of logic components that are currently not in use. Clocking is enabled again based on incoming stimuli data and/or signals to that logic component. Dynamic clock gating is a fine grained mechanism to enable and disable clock signals. The switching of the clocking can very well occur within hundreds of cycles.
The implementation of dynamic clock gating in logic circuits is disclosed in the IBM-Paper “Design and Implementation of the POWERS Microprocessor” by Joachim Clabes et al, DAC 2004, Jun. 7-11, 2004, San Diego, Calif., USA, May 1, 2008, Pages 670-672, for example. Dynamic clock gating reduces the switching power with no impact on frequency or performance. However, dynamic clock gating adds additional complexity to the logic circuit design which has to behave completely independent on the dynamic clock gating configuration. Independent in this context means that cycle accurate behavior is guaranteed on all interfaces and on hardware traces.
The goal of verification of logic circuit designs is to identify problems early in the product development cycle, fix an identified problem in the design, and rerun the verification process on the modified logic circuit design. A major part of the verification effort is called functional verification. Its purpose is to verify the functional correctness of the logic circuit design. Simply put, the logic circuit does compute a corresponding correct result based on any valid input data. A proven and efficient methodology to achieve that goal is called biased random simulation. It is based on the idea of driving random but valid stimuli data on the interfaces of the design under verification. In order to be able to reproduce test cases, i.e. for debugging, all stimuli data are derived from one seed. Simulation means compute state transitions of the logic circuit design which result in changes on corresponding output signals of the logic circuit design. All changes in interface signals and/or data are observed by the verification environment and are used to make predictions and compare those predictions to the real behavior of the device under verification. Errors are flagged if the predictions and the real behavior are not equal. This approach relies on interface signals and/or data only and, for example, does not check performance behavior of the logic circuit design that is not described by the interface specification.
Functional verification methods of logic circuit designs using dynamic clock gating are disclosed in the IBM-Paper “Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems” by D. W. Victor et al, IBM J. RES. & DEV. VOL. 49, NO. 4/5, July/September 2005, Pages 541-553, and in the IBM-Paper “Functional formal verification on designs of pSeries microprocessors and communication subsystems” by R. M. Gott et al, IBM J. RES. & DEV. VOL. 49, NO. 4/5, July/September 2005, Pages 565-580, for example.
The described state of the art functional verification methods can not verify the design goal for logic circuit designs using dynamic clock gating to behave completely independent on the dynamic clock gating configuration. The state of the art verification methods only guarantee functional correctness of the logic circuit design and are not able to detect any changes in the behavior of the logic circuit design based on the dynamic clock gating configuration that could result in serious performance degradations.
An example of problems which could arise in a logic circuit design due to dynamic clock gating the Least-Recently-Used-Algorithm (LRU-Algorithm) of a cache is mentioned here. Assume that a cache is twelve way associative. Due to a clock gating problem the behavior of the LRU-Algorithm can be changed in a problematic way. The ultimate goal that the oldest cache line is chosen to be replaced by a new line does not work anymore, but a more recent line is chosen. For example, in our case the behavior changed in a way that the cache behaved as a two way associative cache only, resulting in a significant reduction in system performance.
Another example of problems which could arise in a logic circuit design due to dynamic clock gating is an arbiter. Here, incoming requests need to be prioritized in an appropriate manner to ensure good performance. In a worst case scenario, hangs, i.e. no forward progress, could occur. While hangs are already detected via the biased random stimuli data in known verification environments, performance related topics are not necessarily detected.
These two scenarios are just two examples. There are many of those in a cache design. So in previous verification environments or verification methods the impact of dynamic clock gating on the above mentioned items is not considered.